Datapath in Arithmetic and Logic Unit (ALU) Research Paper

Introduction

Arithmetic and Logic Unit (ALU) refers to the circuitry in the Central Processing Unit that is responsible for performing arithmetical computations and logical operations. Arithmetic computations performed by ALU can be in the form of multiplication, addition and subtraction and comparison functions. Logic operations performed by the AKU include AND, OR, XOR and NOR (Hwang 2006).

A datapath refers to a group of functional elements in a Central Processing Unit that has the responsibility of performing operations related to data processing. The principal function of a datapath is to link up the functional units by means of data routes. Data paths can be integrated together to increase the size of the data paths by use of multiplexers (Stallings 2006).

Arithmetic Logic Unit Decoder (ALUdec) refers to the component of the ALU that takes the data bits found in the instruction register and performs the necessary decoding by specifying the operands and functional operations to be performed according to the instructions.

Programmable Logic Array (PLA) is a digital device that is programmable and used in the implementation of combinational logic circuits. The PLA comprises of a series of AND gate planes that are programmable, which can be connected to other OR gates that programmable in order to generate the desired output (Godse 2010). One of the principal functions of the PLA is to facilitate datapath control, in the sense that it helps in the definition of various states of the instruction, by use of conditional branching; the desired datapath can be predetermined (Stallings 2006).

Controller refers to the circuitry in the CPU that has the principal function of controlling the way information moves within the processor. In addition, the controller has the necessary architectural circuitry such that it is capable of controlling other functional units of the Central Processing Unit. It is therefore considered to the brain of the CPU, which in turn controls the whole computer (Stallings 2006).

Processes of datapath design and controller design

Datapath design and controller design serves the fundamental purpose of controlling the Arithmetic and Logic Unit. The datapath unit usually comprises of Arithmetic Units, Control Units, Control-dataflow sequential Machine, Algorithm State Machines (ASM) charts that has the state box, decision box and the conditional output box. The following are the design issues that must be put into account when controlling the Arithmetic Logic Unit (Hwang 2006):

1. All the combinational logic circuits must be in placed in a continuous manner or a block arrangement;
2. All the input signals must appear on the sensitivity list of the continuous arrangement;
3. Every datapath in the block arrangement must be assigned a value with the precise set of bits.

The following are the steps in the design of controllers

1. The instruction set, instruction types and format form the entry point for the design. There are three types of instruction formats, which are the R-type, Branch and Load
2. The registers that are to be read are specified using rs and rt; which are found in the bit positions [25:21] and [20:16] respectively
3. The base register used for loading and storing the instructions are specifies in rs, [25:21]
4. The bit position [15:0] specifies the 16-bit offset for load and store;
5. The destination register can be implemented in either position [20:16] for load, while [15:11] for R-type instruction formats. A multiplexer is required to select the field that the instruction will use to indicate the number of register that has to be written (Stallings 2006).

Improvements to the design

One of the most important improvements to the design is that the design should incorporate the concept of reconfiguration of the datapath; this can be achieved by imprinting the datapath on a fabric in such a manner that it can be adjusted during the actual run time. This aspect facilitates additional efficiency in CPU processing (Hwang 2006).

References

Godse, A. (2010). Computer Architecture. New York: Technical Publications.

Hwang, E. (2006). Digital LOgic and Microprocessor design with VHDL. New York: Thomson.

Stallings, W. (2006). Computer Organization and Architecture: Designing for Performance. New York: Prentice Hall.